1. Field of the Invention
The present invention relates to a method for fabricating a vertical transistor, and more particularly, to a method for fabricating a vertical transistor which is suitable for minimizing the size of a semiconductor device.
2. Discussion of the Related Art
With high integration of a semiconductor device, a size of the semiconductor device decreases, whereby a channel length of the semiconductor device also decreases. The decrease of the channel length in the semiconductor device may result in undesirable electric characteristics, for example, a short channel effect.
In order to overcome the short channel effect, it is necessary to realize a vertical decrease in the size of the device, such as a decrease in a thickness of a gate insulating layer and a junction depth of source/drain, as well as a horizontal decrease in the size of the device, such as a decrease in a length of a gate electrode. Also, according to the horizontal and vertical decrease, an applied voltage decreases and a doping density of a semiconductor substrate increases. Thus, there is a requirement for the effective control of a doping profile of a channel region.
However, despite the decrease in the size of the semiconductor device, the operational power needed for the electronic equipment has not decreased. For example, in case of an NMOS transistor, electrons provided from the source are excessively accelerated in state of a high potential gradient, whereby hot carriers generate. Accordingly, an LDD (Lightly Doped Drain) structure having an improved NMOS transistor has been researched and developed.
In the LDD-structure transistor, a lightly-doped n-type (n−) region is positioned between a channel and a highly-doped n-type (n+) source/drain. The lightly-doped n-type (n−) region buffers a high drain voltage around the drain junction. Thus, it is possible to prevent inducement of a potential gradient, thereby preventing the generation of hot carriers. Based on research for technology of high-integration semiconductor devices, various methods for fabricating a MOSFET of the LDD structure have been proposed. Among them, the method for forming the LDD structure by forming spacers at sidewalls of the gate electrode is most generally used.
However, due to high integration in semiconductor devices, it is hard to control the short channel effect with the LDD structure. Accordingly, to satisfy this request for the optimal structure of minimizing the short channel effect, a vertical transistor is proposed. A vertical transistor is suitable for realizing a minimum size for the semiconductor device by decreasing the channel length.
In the vertical transistor, the channel region is formed in the vertical direction. The channel length is determined dependent on not a width of an active region, but a thickness of the active region. As compared with a conventional horizontal transistor, the vertical transistor has the advantageous characteristics such as a decrease in the channel length without photolithography.